1( a) illustrates an exemplary system for scan testing an integrated circuit (IC) using an ATPG system, in accordance with an embodiment of the present subject matter.įIG. For simplicity and clarity of illustration, elements in the figures are not necessarily to scale.įIG. The same numbers are used throughout the drawings to reference like features and components. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The detailed description is provided with reference to the accompanying figures. In an implementation, the second clock domain is provided with the capture pulses at the second fast clock after the first clock domain has been tested. The capture pulses at the second fast clock are provided based on a delayed scan enable signal. A second clock domain of the IC is then provided with capture pulses at a frequency of a second fast clock. The capture pulses launch and capture the response of the first clock domain to a test pattern. The capture pulses at the first fast clock are provided based on a scan enable signal. In one embodiment, the method includes providing capture pulses at a frequency of a first fast clock to test a first clock domain of the IC. This summary is not intended to identify essential features of the claimed subject matter nor is it intended for use in determining or limiting the scope of the claimed subject matter. This summary is provided to introduce concepts related to testing of multi-clock domains of an integrated circuit (IC), which are further described below in the detailed description. Additionally, even though the ATPG tools may theoretically satisfy the power budget requirements for all the clock domains, the ATPG tools inaccurately report the switching activity for an individual clock domain. This translates into lesser flexibility in choosing the test patterns and reduced test coverage. The ATPG tools generally assign a combined power budget for all the clock domains. However, multiple clock domains, i.e., logic circuits operating at different clock frequencies, often exist within a single IC. The above mentioned methodology works well for ICs having a single clock domain or a plurality of clock domains whose clocks are derived from a single clock source. the switching activity, in response to a test pattern does not exceed the specified power budget. For example, the ATPG tools target a limited number and limited types of faults such that the number of memory elements toggling, i.e. Therefore, the low-power ATPG tools deterministically generate the test patterns to keep the switching activity below the specified power budget. This can result in false failures and in some cases affect product reliability or cause permanent damage to the IC.Ĭontrolling the switching activity during testing to stay within the specified power budget is desired for any low-power ATPG tool. As a result, the nature of the test patterns may be such that the switching activity in the IC may be more than a specified power budget, for example, the switching activity may be 10% or more of the total possible switching per clock pulse. The goal for any ATPG tool is to achieve the maximum test coverage with minimum number of test patterns. Various types of test patterns are provided for testing faults, such as, stuck-at faults, transition faults, and path-delay faults.ĭuring testing, the number of test patterns and execution time of testing are tracked to minimize the overall cost of testing. Such ICs are typically tested using Automatic Test Pattern Generation (ATPG) tools, which simulate the overall functionality of an IC and generate test patterns, also referred to as test vectors. With the advent of sub-micron technology, integrated circuits (ICs) are becoming increasingly dense making them suitable for low power and low cost applications. The present invention relates to testing of integrated circuits, and in particular, relates to testing of multi-clock domains. 23, 2010, which is incorporated herein in its entirety by this reference.
The present application claims priority of India Patent Application No.
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